Join Us at DAC and See the Latest Developments In Ascent Static Verification and Meridian Sign-off  
  You are invited to visit Real Intent in booth #928 at the 54th DAC show in Austin.  

Real Intent is known for having the fastest, highest-capacity verification tools for early functional verification with static RTL analysis, and for advanced RTL sign-off of designs with multiple clock and reset domains.

Complete our quick verification survey at the booth and you will be entered into drawings for a Roku 4 streaming player and an Amazon Echo wireless speaker and voice commander!

To celebrate faster verification and design, enjoy a modern, high-speed espresso coffee from our DeLonghi Magnifica automatic coffee machine.

Our technical presentations will bring you up to date with our new product releases that have been proven on giga-gate SoC and FPGA designs. Click on the links below to book your appointment with Real Intent at booth #928.

  Accelerate Your RTL Sign-off  

Real Intent will present the elements of a best-in-class solution for the accelerated RTL sign-off of SoC and FPGA designs. A full suite of static verification risks will be covered including: RTL static and formal intent verification; reset analysis and optimization; CDC sign-off; RDC sign-off and X-safe design analysis. Schedule a Time.

  Most precise static and formal RTL Analysis with Ascent Lint and AutoFormal  
  Meridian CDC continues to be the fastest, highest capacity and most precise CDC sign-off solution in the market. At DAC 2017, we present industry’s best Hierarchical CDC capability that allows users to perform CDC verification on billion-gate SOCs within a matter of hours. The flow enabled by transparent model database provides unprecedented productivity gains, high accuracy, and low noise results with seamless SoC debug. You will not want to miss seeing the latest in advanced CDC sign-off. Schedule a Time.  
  Meridian CDC with Hierarchical CDC flow  
  Real Intent will present the elements of a best-in-class solution for the accelerated RTL sign-off of SoC and FPGA designs. A full suite of static verification risks will be covered including: syntax and semantic checking (lint); constraints and exception verification; reset analysis and optimization; automatic intent verification; CDC sign-off; and X-safe design analysis.Schedule a Time.  
  Ascent XV with Advanced Gate-level Pessimism Analysis  
  Ascent X-Verification System (XV) provides a comprehensive static solution for making an RTL design X-robust and eliminates error-prone debug at the netlist level. At DAC, discover the very latest in X-propagation verification. See how to identify unnecessary resets at RTL. Learn a cost effective approach for tackling pessimism accurately in your gate level simulations. Schedule a Time.  
  Introducing industry’s most accurate Reset Domain Crossing solution  
  Meridian RDC is the lowest noise and most precise reset domain crossing sign-off tool in the market. It performs efficient and thorough static analysis to ensure that signals crossing reset domains function reliably. Among other things, it identifies metastability problems arising from software and/or low power resets. Meridian RDC is the only solution that considers cascading effects of improper reset design and enables comprehensive reset domain crossing sign-off. Schedule a Time.  
  Gate-Level CDC Sign-off with Meridian Physical CDC  
  RTL CDC sign-off assumptions may not be valid because of logic synthesis and power optimizations. Meridian Physical CDC is the only solution that ensures complete gate-level sign-off. See how a new architecture leverages results of RTL CDC sign-off and performs efficient and incremental CDC analysis at gate level.Schedule a Time.


For more information, visit

Real Intent, Inc. 990 Almanor Ave., Suite 220, Sunnyvale CA
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